`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:36:11 09/27/2011 
// Design Name: 
// Module Name:    REG_ALU_LOGIC 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module REG_ALU_Pipelined(CLK, reset, reg1, reg2, wr_en, write_address, op, regin_data, regin_en, result_en, imm_data, imm_en, F_out, PSR_en, result_out, B_out);

	input CLK, reset, wr_en, imm_en, regin_en, result_en, PSR_en;
	input [3:0] reg1, reg2, write_address;
	input [7:0] op;
	 
	input [15:0] imm_data, regin_data;
	 
	output [4:0] F_out;
	wire [4:0] F;

	wire [15:0] result,regin;
	wire [15:0] A,B_in,B;
   output [15:0] result_out, B_out;

	
	mux21_16bit reg_write_mux(result,regin_data,regin,regin_en);
 	mux21_16bit Bimmediate_mux(B,imm_data,B_in,imm_en);
	
	register5 PSR_reg(F,F_out,PSR_en,reset,CLK);
	
	assign B_out = B;
	

   //ALU Result buffers
	//TristateBuffer result_buf(result,result_out,result_en);
	
	mux21_16bit result_mux(16'h0000,result,result_out,result_en);


	//Writedata in and out are created so that an imediate value can be passed in instead of value b from the register.
	Regfile registers(CLK, reset, reg1, reg2, A, B, wr_en, write_address, regin);

	//ALUUnit(A, B, op, result, F, Cin);

	ALUUnit alu(.A(A), .B(B_in), .op(op), .result(result), .F(F), .Cin(1'b0));

	

endmodule
